In an SMP Computer System data may be partitioned across one or more chips. For instance, on planned future systems being developed, the computer system has Quadword data buses between the system controller SC and the central processor functional units CPs. For a given SC, the Quadword is partitioned into two chips, each with a doubleword. Each doubleword has ECC protection across it.
The problem is that the data may get corrupted due to a control error without causing the ECC to be bad. For instance, if one dataflow chip had a defect that caused it to send a doubleword from an incorrect source, the data will still have good ECC. Therefore, the problem would go undetected. In past tries to provide a solution to this problem, cross-checking was usually performed using a prior art parity generation and compare circuit as illustrated by FIG. 1. The problem with this is that it only detects single-bit or odd-number-bit failures in the control words. With control problems, often more than one bit can mismatch (eg. A bad decode will cause one signal to come on while another will turn off). To do any more extensive compare (like a full bus compare) would require a great deal of chip I/O. In planned systems (and most systems in the SMP industry) this is not feasible.